PCB Thickness Measurement
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PCB Thickness Measurement – IPC‑TM‑650 Cross‑Section, Micrometer & Impedance Control for Multilayer Reliability
Overall PCB thickness and layer‑to‑layer dielectric thickness directly control impedance, breakdown voltage, and mechanical rigidity. A thickness deviation of just ±10% can shift characteristic impedance by ±5–8 Ω, causing signal integrity failures in high‑speed designs. Moreover, inconsistent dielectric thickness between layers leads to differential pair skew and via stub resonance. IPC‑TM‑650 2.4.17 (micrometer measurement) and 2.1.1 (microsection) provide standardized methods to verify overall thickness and individual dielectric layers. Without rigorous thickness control, impedance‑controlled boards may pass electrical test at room temperature but fail under thermal cycling or humidity absorption.
Contents
Engineering Risk Summary
PCB thickness measurement is the verification of overall board thickness and individual dielectric layer heights. These dimensions directly influence controlled impedance (Z₀ ∝ 1/√(Dk) × ln(1.9h/w)), breakdown voltage, and mechanical stiffness. The critical failure thresholds are: overall thickness tolerance >±10% of nominal, or individual dielectric layer variation >±15% for impedance‑critical layers. In high‑speed digital designs (>5 Gbps), a 0.025 mm change in dielectric thickness can shift impedance by 3–5 Ω, causing eye closure and increased jitter. Boards that pass electrical test at one temperature may fail under thermal cycling because dielectric expansion/contraction is not uniform when initial thickness is off‑target.
Failure Mechanism Nodes
Three independent causes of thickness‑related failures.
| Node | Root Cause | Detection Signature | Reliability Consequence |
|---|---|---|---|
| T1: Prepreg thickness variation | Inconsistent resin content, poor press cycle control, or glass style mismatch | Microsection shows dielectric thickness variation >±15% across panel | Impedance mismatch, differential pair skew |
| T2: Copper plating thickness imbalance | Uneven plating current density (PTH vs surface), excessive over‑plating | Cross‑section shows surface copper thickness >50% of specification | Dielectric height reduced, impedance lower than target |
| T3: Laminate core thickness drift | Core supplier variation, moisture absorption, or thermal expansion during lamination | Micrometer measurement shows core thickness out of IPC‑4101 tolerance | Impedance drift across different board lots |
IPC‑TM‑650 Test Method Mapping
Each method defines measurement rules, acceptable ranges, and failure boundaries.
| Method | Measurement Rule | Acceptable Range (Class 3) | Failure Criterion |
|---|---|---|---|
| 2.4.17 Overall Thickness (Micrometer) | Measure at 4‑6 points per panel, average and minimum recorded | Within ±10% of nominal (or ±0.1 mm for boards >1.6 mm) | Deviation >±15% or any point >±10% after statistical adjustment |
| 2.1.1 Microsection (Dielectric Thickness) | Measure each dielectric layer at 3 locations per cross‑section | Individual layer thickness within ±15% of nominal (impedance layers: ±10%) | Any layer out of tolerance → impedance likely fails |
| 2.4.15 Plating Thickness (Microsection) | Measure copper thickness on surface and in PTH barrel | Surface copper: ±20% of nominal; PTH barrel: ≥20 µm | Excessive plating changes dielectric height beyond tolerance |
| 2.4.27 Laminate Thickness (for core materials) | Micrometer measurement of uncored laminate | Per IPC‑4101 slash sheet (typically ±10%) | Out of tolerance → core substitution risk |
Risk‑Weighted Engineering Decision Matrix
Each thickness deviation is evaluated by impact on impedance / signal integrity and manufacturing consistency.
| Condition | Overall Thickness Deviation | Dielectric Layer Variation | Decision | Action |
|---|---|---|---|---|
| Excellent control | ≤±5% | ≤±8% | Accept | Standard production |
| Controlled | ±5‑10% | ±8‑12% | Monitor | Track SPC, verify impedance on test coupon |
| Marginal | ±10‑15% | ±12‑18% | Re‑design / Re‑qualify | Adjust stackup tolerance, require tighter prepreg control |
| Unacceptable | >±15% | >±20% | Reject lot | Scrap; supplier corrective action |
Engineering decision rule: For impedance‑controlled layers, dielectric thickness tolerance must be ≤±10% of nominal. For non‑impedance layers, ±15% is acceptable. Overall thickness tolerance for assembly (SMT) is ≤±10%.
Supplier Audit Layer – How to Detect Hidden Thickness Risks
Related Engineering Resources
Engineering FAQ
Q: Why is overall PCB thickness tolerance important beyond assembly fit?
A: Overall thickness directly controls impedance (through dielectric height), thermal capacitance, and mechanical stiffness. A board that is too thin may warp; too thick may not fit connectors. For impedance lines, the dielectric thickness between reference planes is critical.
Q: What is the typical tolerance for impedance‑controlled dielectric layers?
A: IPC‑6012 Class 3 requires ±10% for dielectric thickness on impedance layers. Some high‑speed designs (≥25 Gbps) demand ±8% or tighter. Achievable with spread‑glass prepreg and strict press control.
Q: Can I rely only on overall thickness measurement (2.4.17) to qualify dielectric consistency?
A: No. Overall thickness hides layer‑to‑layer variation. You must microsection (2.1.1) to verify each dielectric layer, especially for multilayer boards (>8 layers) where individual prepregs may vary.
Q: How does copper plating thickness affect dielectric height?
A: Excessive surface plating (e.g., 50 µm instead of 35 µm) physically reduces the dielectric gap between conductor and reference plane, lowering impedance. Always measure post‑plating dielectric height in microsection.
Q: What is the difference between prepreg thickness and core thickness?
A: Core is fully cured laminate with copper on both sides; its thickness is stable. Prepreg is partially cured and flows during lamination; its final thickness depends on resin content, press pressure, and adjacent copper features. Microsection is the only way to verify post‑lamination prepreg thickness.
Supplier Audit Checklist (IPC‑TM‑650 Based)
- Overall thickness per 2.4.17 – within ±10% of nominal, measured at ≥4 points per panel
- Microsection (2.1.1) on 2 panels per lot – dielectric layer thickness recorded for each impedance layer
- Individual dielectric layer tolerance: impedance layers ≤±10%, non‑impedance ≤±15%
- Copper plating thickness per 2.4.15 – surface copper within ±20% of nominal
- Prepreg resin content certificates – Cpk ≥1.33 for used prepreg types
- Impedance test coupon included on each panel – TDR measured and correlated to dielectric thickness
- Incoming lot sampling: 2 panels/lot, verify overall thickness
- Requalification triggers: prepreg lot change, press maintenance, new core supplier
Need to qualify a PCB supplier for impedance‑controlled designs?
Our lab performs dielectric thickness measurement, microsection, and TDR correlation per IPC‑TM‑650.
Request Thickness & Impedance Analysis →IPC‑TM‑650 Methods: 2.4.17 (Overall Thickness), 2.1.1 (Microsection Dielectric), 2.4.15 (Plating Thickness), 2.4.27 (Laminate Thickness). Related standards: IPC‑6012 Class 3, IPC‑4101, IPC‑2141A.
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