Castellated Hole / Half Hole
Edge-plated half holes for modules and board-to-board connections.
PCB Technology & Capabilities
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Castellated Hole / Half Hole — Process Capabilities & DFM Guide
Castellated edges turn modules into solderable “SMD headers,” enabling quick SMT attach, easy inspection, and strong mechanical anchoring—ideal for RF/IoT modules, power daughterboards, and pre-certified wireless cards.
Process Capability Matrix（Finished Spec）
|
Item |
Typical |
Premium (upon review) |
Notes |
|
Finished half-hole Ø (original drill) |
≥0.35 mm |
0.35 mm |
Smaller sizes increase burr risk |
|
Pitch (center-to-center) |
≥0.50 mm |
≥0.45 mm |
Keep solder mask off gaps |
|
Annular ring (finished) |
≥0.20 mm |
≥0.15 mm |
After etch/plating compensation |
|
Hole wall copper |
≥20 µm |
≥25 µm |
Uniformity critical at cut edge |
|
Surface finish |
ENIG / ENEPIG |
— |
HASL possible but less uniform |
|
Edge milling tool |
0.8–1.6 mm |
— |
Tool radius defines notch shape |
|
Edge-to-inner copper |
≥0.25–0.30 mm |
≥0.20 mm |
Prevent plane exposure |
|
Board thickness |
0.6–2.0 mm |
0.4–3.2 mm |
Thin cores require panel support |
DFM & Padstack Rules（Designer-Ready）
- Padstack: Through-hole pad with finished AR ≥0.20 mm; keep solder mask clearance ≥0.10–0.15 mm from scallop rim.
- Cut line: Program the milling path through hole centers (≈50% cut) to form consistent half-moons.
- Copper keep-out at edge: Inner planes/pours set back ≥0.25–0.30 mm from board edge.
- Finish: Prefer ENIG/ENEPIG for wetting and inspection; avoid HASL bridging when pitch <1.0 mm.
- Fiducials: Place local fiducials near castellated edges to stabilize routing accuracy.
- Mechanical tie-in: Add corner tooling holes/stiffeners or edge tabs for panel stability.
Manufacturing Flow & Controls
PTH drill → Desmear/PTH Cu seed → Pattern plate (hole wall Cu build) → Finish (ENIG/ENEPIG) → Edge routing to cut through holes → Deburr / micro-chamfer → Final clean & AOI → 100% visual for continuity and burrs.
Controls: Tool wear & run-out, burr/tear at copper rim, continuity of Cu/Ni/Au at exposed half-barrels, edge fiber pull-out control.
Quality & Acceptance（IPC Reference）
- Continuity: Cu/Ni/Au must be continuous across the exposed half-barrel (visual + cross-section sampling).
- Burrs/tears: None visible; micro-chamfer 0.05–0.15 mm acceptable.
- Solderability: Wetting verified via module reflow test; bridge-free fillet profile expected.
- Reference: IPC-A-600 Class 2/3 (edge condition), IPC-6012 acceptance for PTH integrity.
Typical Applications
RF/IoT modules (Wi-Fi/BT/LTE/LoRa), GNSS, power daughterboards, sensor carriers, USB/UART bridges, castellated DevKit boards.
Common Issues → Countermeasures
- Burrs/rough scallops → Sharper tool, reduced feed near holes, add micro-chamfer pass.
- Inner copper exposure → Increase edge keep-out; verify layer registration before routing.
- Poor wetting/bridging → Switch to ENIG/ENEPIG; widen pitch or increase mask clearance.
- Cracked half-barrel → Increase hole wall Cu; verify plating uniformity before routing.
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