Controlled Impedance
Controlled impedance structures for high-speed and RF signals.
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Controlled Impedance — Process Capabilities & DFM Guide
Consistent impedance means cleaner eyes, lower jitter, and predictable margins. We co-optimize stack-up, geometry, and process to meet spec the first time and verify it with TDR coupons.
Capability Tiers（Tolerance & Materials）
|
Tier |
Typical Materials |
Target Tolerance |
Notes |
|
Standard |
FR-4 / Low-loss FR-4 |
±10% |
General high-speed digital |
|
Tight |
Low-loss FR-4 / Hydrocarbon |
±5–8% |
Most data-center / AI server |
|
RF Precision |
Hydrocarbon / PTFE |
±3–4% |
RF front-end, phased arrays |
Supported Transmission Structures
|
Structure |
Mode |
Typical Targets |
|
Surface Microstrip |
SE / Diff |
50 Ω、40 Ω SE；80、90、100 Ω Diff（USB3/HDMI） |
|
Stripline / Dual Stripline |
SE / Diff |
50 Ω、40 Ω SE；80、90、100 Ω Diff（PCIe），100 Ω Diff（Ethernet/SATA） |
|
Coplanar Waveguide (CPW) |
SE / Diff |
For denser routing & isolation |
|
Embedded Microstrip (solder mask over) |
SE / Diff |
Mask lowers Z₀ slightly—compensate in design |
Process Capability Matrix（Geometry & Stack-up）
|
Item |
Capability (Typical) |
Notes |
|
Controlled width |
≥ 2.5 mil (63 µm) |
Can go down to ~2.0 mil for HDI, subject to collaboration review |
|
Controlled spacing (Diff) |
≥ 3.0 mil pair gap |
Tighter spacing requires review for coupling and manufacturing tolerance |
|
Dielectric thickness control |
±8–10% panel-to-panel |
Press flow & glass style managed |
|
Copper roughness class |
Modeled (Huray/Hammerstad) |
Entered in field solver |
|
Solder mask effect |
−1~−3 Ω on microstrip |
Mask type/thickness accounted |
|
Backdrill residual stub |
≤ 0.20 mm (typ.) |
Critical channels ≤ 0.15 mm, subject to review |
|
Plane continuity |
100% under HSD pairs |
Return path via stitching |
DFM Rules（Designer-Ready）
- Keep-outs: ≥15 mil from impedance traces to splits/plane edges; ≥25 mil to high-edge-rate clocks.
- Via strategy: Use backdrill or HDI microvias on high-speed layers; minimize via count per pair; add return vias next to signal vias.
- Length matching: Intra-pair ≤5 mil（125 µm）; inter-pair per interface spec.
- Mask strategy: For microstrip, prefer solder mask over only if modeled; otherwise keep a narrow solder-mask clearance to stabilize process.
- Copper balance: Use thieving/mesh to control etch bias and plating uniformity.
- Reference planes: No slots/splits under diff pairs; if must cross, use GND bridge vias.
Manufacturing Flow & Controls
Stack-up proposal → Field solving (geometry & roughness) → Coupon design (SE/Diff) → LDI imaging & etch compensation → Pattern plate uniformity control → Backdrill program & verify → TDR coupon test → SPC release.
Typical Targets by Interface
|
Interface |
Mode |
Target |
|
USB 3.x |
Diff |
90 Ω ±10% |
|
HDMI / SATA / Ethernet |
Diff |
100 Ω ±10% |
|
PCIe Gen4/5/6 |
Diff |
80 Ω ±10% |
|
USB 2.0 HS |
SE |
40 Ω ±10%（on-board, short） |
|
RF chains |
SE / Diff |
Per design (often 50 Ω SE) |
Common Issues → Countermeasures
- Z₀ out of spec → Re-solve with actual copper/thickness; adjust width/space; refine mask strategy.
- Mode conversion / skew → Tighten pair symmetry; reduce stub; pair-via co-location.
- Loss higher than model → Update roughness model; check resin content/glass style; evaluate finish choice.
- Reflections at connectors → Improve pad transition, anti-pad shapes, via-in-pad with backfill.
Quality Standards & Test Methods
- Design methods：Industry practices aligned with IPC-2221/2222 & impedance design guides.
- Acceptance：IPC-6012（impedance acceptance on coupons, Class 2/3 as required）。
- Test：TDR methods per IPC-TM-650 family; in-house fixtures for SE/Diff coupons.
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