Engineering Decision Brief
Allocate the channel budget first—then verify what fabrication can change
A 112G PAM4 loss budget should connect the SerDes or compliance limit to the actual PCB stackup, copper profile, via transitions, connector launches and manufacturing tolerances. The design model defines the target; fabrication review determines whether that target can be repeated in production.
How much channel loss remains available for PCB traces after packages, connectors and vias are allocated?
Material Df, copper roughness, impedance variation, via stubs and backdrill depth control.
A project-specific coupon and inspection plan agreed before prototype or production release.
1. Build the 112G PAM4 Loss Budget from the System Limit
The correct starting point is not a generic “maximum PCB loss” number. Start with the electrical limit defined by the selected silicon, interface specification or compliance model, then reserve margin for every non-PCB element before assigning the remainder to the board.
= Total channel loss limit
− Tx/Rx package and launch allocation
− Connector allocation
− Via-transition allocation
− Manufacturing and correlation reserve
Illustrative allocation example
| Budget Item | Illustrative Allocation | Engineering Input Required |
|---|---|---|
| Total channel limit at the evaluation frequency | 30 dB example only | SerDes vendor data, interface specification or compliance model |
| Tx/Rx packages and board launches | 4 dB | Package models, breakout geometry and launch simulation |
| Connectors | 4 dB | Connector S-parameters, mating configuration and launch design |
| Via transitions | 2 dB | Via count, antipad geometry, residual stub and reference-plane transitions |
| Manufacturing and correlation reserve | 2 dB | Material variation, etch variation, copper profile and test correlation |
| Remaining PCB trace budget | 18 dB | Trace length, routing layer, dielectric loss and copper roughness model |
Replace every illustrative value with project-specific data before design release.
Decision rule
If the calculated trace budget cannot support the required routing length, the solution is usually a combination of shorter routing, lower-loss material, lower-profile copper, fewer transitions or a different connector/channel architecture—not simply a tighter impedance tolerance.
2. Material Selection: Review Df, Dk Stability and Construction Together
Material selection affects insertion loss, impedance, propagation delay and build-to-build consistency. The laminate name alone is not enough; the stackup must be evaluated using the specific dielectric thickness, resin system, glass construction and copper profile intended for production.
| Material Variable | Channel Effect | What to Confirm Before Fabrication |
|---|---|---|
| Dissipation factor (Df) | Directly influences dielectric loss | Frequency-dependent model, test method and production material designation |
| Dielectric constant (Dk) | Influences impedance and propagation delay | Design Dk versus datasheet Dk, target thickness and impedance model |
| Glass weave and resin content | Can influence skew and local effective Dk | Glass style, routing orientation and construction availability |
| Material substitution | May change loss, impedance and lamination behavior | Equivalent construction, copper compatibility and revalidation requirements |
| Lot and thickness variation | Can shift impedance and insertion loss | Incoming material control, press plan and finished dielectric tolerance |
Avoid a common specification error
Do not approve an alternate material only because its nominal Dk and Df look similar. Confirm copper type, glass construction, resin content, available dielectric thicknesses and the need to rerun the impedance/loss model.
For a broader manufacturing view, review UltroNiu’s high-speed PCB manufacturing capabilities and high-frequency material and stackup support.
3. Copper Roughness: Model the Actual Foil, Not a Generic Surface
At 112G PAM4 frequencies, conductor loss is sensitive to the copper surface profile. A lower-profile foil can improve channel loss, but the correct decision must also consider adhesion, lamination reliability, etching behavior, cost and production availability.
| Copper Review Item | Why It Matters | Required Project Input |
|---|---|---|
| Foil designation | ED, RTF, VLP and HVLP descriptions are not interchangeable across suppliers | Exact laminate/foil construction and supplier documentation |
| Roughness model | Changes predicted conductor loss | Model type and parameter set used by the SI team |
| Treated versus untreated side | The signal trace can interact with different surface profiles | Layer construction and foil orientation |
| Adhesion and process window | Very low-profile copper still has to survive lamination and reliability testing | Material supplier process recommendations and qualification plan |
| Production consistency | Lot variation can affect model-to-hardware correlation | Incoming documentation and agreed verification method |
Use the dedicated guides on copper roughness selection thresholds and HVLP, VLP and ED copper loss comparison for deeper material analysis.
4. Backdrill Control: Define the Residual Stub from the Channel Model
Backdrilling reduces unused plated-through-hole barrel length. It can improve return loss and reduce resonant behavior, but the residual stub target should be derived from the channel model and then translated into a manufacturable drill-depth window.
Define the electrical target
Use simulation or compliance analysis to determine the maximum acceptable residual stub for each critical transition.
Translate it into a drill window
Account for finished board thickness, dielectric variation, layer registration and controlled-depth drilling tolerance.
Document the backdrill table
Identify drill side, target layer, affected holes, depth reference and inspection requirement.
Verify the fabricated structure
Use the agreed combination of X-ray, microsection, coupon measurement or channel testing.
| Backdrill Variable | Risk if Undefined | Review Output |
|---|---|---|
| Signal transition layer | Incorrect depth reference | Approved backdrill layer map |
| Finished board thickness | Residual stub shifts after lamination | Thickness tolerance included in depth calculation |
| Layer registration | Risk of drilling too shallow or too deep | Manufacturable depth window and inspection plan |
| Via, pad and antipad geometry | Unexpected impedance discontinuity | Reviewed transition structure |
| Residual stub requirement | Ambiguous acceptance criteria | Project-specific maximum and measurement method |
Related engineering pages: when 112G designs require backdrilling and how to determine an acceptable residual stub.
5. ILD, Via Transitions and Connector Launches Can Consume Margin Differently
Absolute insertion loss is only one part of channel behavior. Insertion loss deviation (ILD), localized resonances, return-loss discontinuities and mode conversion can reduce margin even when the total loss number appears acceptable.
| Channel Feature | What Can Go Wrong | Review Method |
|---|---|---|
| Insertion loss deviation | Ripple or notches reduce equalization effectiveness | Frequency-domain review and model-to-measurement correlation |
| Via transition | Antipad, reference-plane and stub discontinuities | 3D model, TDR and/or S-parameter analysis |
| BGA breakout | Return-path break, neck-down and skew | Layout/stackup review and transition modeling |
| Connector launch | Reflection, crosstalk and mode conversion | Vendor model plus board-specific launch analysis |
| Coupon-to-product mismatch | Passing coupon does not represent the real channel | Coupon topology matched to critical routing and transitions |
What the PCB supplier should receive
Provide the critical routing layers, target impedance, maximum channel length, transition count, backdrill requirements, connector locations and the verification method expected for prototype and production builds.
6. Manufacturing Variation: Reserve Margin for What the Model Idealizes
Simulation commonly uses nominal geometries and material values. Production introduces controlled variation in dielectric thickness, etched trace geometry, plated copper, registration and drilling depth. The loss budget should include a reserve for these effects and for model-to-measurement correlation.
| Manufacturing Variable | Possible Channel Effect | Manufacturing Review |
|---|---|---|
| Finished dielectric thickness | Impedance and delay variation | Press plan, material construction and finished thickness tolerance |
| Trace width and trapezoidal profile | Impedance and conductor-loss shift | Etch compensation and finished geometry target |
| Plated copper thickness | Geometry and impedance shift on outer layers | Finished copper target and process window |
| Material lot and copper profile | Loss correlation variation | Exact material designation and traceability requirements |
| Layer registration | Via, antipad and backdrill alignment risk | Stackup-specific registration review |
| Backdrill depth | Residual stub variation | Depth window, control method and acceptance criteria |
The manufacturing reserve should not be an arbitrary number. It should reflect the maturity of the material set, stackup, channel model, fabrication process and correlation data available for the project.
7. Verify the Budget with a Project-Specific Coupon and Inspection Plan
Verification should be agreed before the board enters production. The required methods depend on whether the project needs impedance confirmation, loss correlation, via-transition validation, residual stub inspection or full channel S-parameters.
| Verification Method | What It Confirms | When to Specify It |
|---|---|---|
| TDR impedance coupon | Single-ended or differential impedance and discontinuities | When controlled impedance and build consistency are critical |
| Δ-Loss or equivalent loss coupon | Insertion loss per unit length and build-to-build correlation | When trace-loss margin is limited or material correlation is required |
| Via or launch coupon | Transition-specific S-parameters or TDR behavior | When via fields, BGA breakouts or connector launches dominate risk |
| X-ray or microsection | Backdrill depth, residual stub and structural condition | When a maximum residual stub is specified |
| Product-level S-parameter measurement | Actual channel performance | When the customer and supplier agree fixtures, de-embedding and acceptance criteria |
Do not write “S2P required” without defining the method
Specify fixture design, reference planes, de-embedding approach, frequency range, file format and acceptance criteria. Otherwise, two valid measurements can still produce results that are difficult to compare.
8. 112G PCB Release Checklist Before Fabrication
A useful fabrication package should allow the PCB manufacturer to connect the electrical intent to the physical stackup and inspection plan.
9. How UltroNiu Supports a 112G Stackup Review
UltroNiu’s role is to review whether the proposed stackup, materials, impedance structures, vias and backdrill requirements can be translated into a controlled PCB manufacturing process. The customer or SI team retains ownership of the system-level channel model and compliance target.
Pre-production engineering review
Review stackup, material availability, impedance structures, via transitions, backdrill notes and fabrication risks.
NPI verification planning
Align coupons, inspection methods, reporting requirements and change-control expectations before the prototype build.
Prototype-to-production control
Maintain approved materials, stackup parameters and critical process requirements as the design moves toward repeat production.
Engineering feedback
Return a risk list covering manufacturability, material substitutions, depth-control concerns and verification gaps.
Frequently Asked Questions
What is the maximum acceptable PCB loss for a 112G PAM4 channel?
There is no universal PCB-loss limit. The allowable board loss depends on the SerDes or compliance limit after package, connector, via-transition and manufacturing reserves are allocated. Use the silicon vendor or interface specification as the starting point.
How does copper roughness affect 112G PCB channels?
Copper roughness increases the effective conductor path and can increase conductor loss at high frequencies. The SI model should use the actual foil construction and roughness parameters planned for production rather than a generic copper assumption.
Does every 112G PCB require backdrilling?
No. Backdrilling depends on the via length, transition layers, residual stub resonance, channel architecture and available margin. It should be justified through simulation, compliance analysis or measurement—not applied as a universal rule.
How should the maximum residual stub be specified?
Derive the electrical target from the channel model, then confirm that the target can be achieved across finished board thickness, layer registration and controlled-depth drilling tolerances. The drawing should also define the measurement or inspection method.
Which materials are suitable for 112G PAM4 PCBs?
Suitable materials require a loss profile, construction and production process that support the project’s channel length and margin. Df, Dk stability, glass construction, copper profile, available thicknesses and substitution risk should be evaluated together.
What verification should be requested from the PCB manufacturer?
The verification plan may include TDR impedance coupons, Δ-Loss or equivalent coupons, via/launch coupons, X-ray or microsection inspection and project-level S-parameter measurements. The exact scope should be agreed before fabrication.
Why can simulation and fabricated PCB results differ?
Simulation uses modeled materials, geometries and transitions. Fabrication introduces real material lots, copper profiles, etched trace shapes, dielectric thicknesses, registration and drilling tolerances. Correlation improves when the model and manufacturing data use the same physical assumptions.
Can UltroNiu review a 112G stackup before quoting?
Yes. Submit the stackup, Gerber or ODB++ data, target impedance, materials, backdrill requirements and project constraints through the engineering review page. The review focuses on manufacturability risks and the information needed for a controlled build.
112G Engineering Review
Submit Your Stackup Before the Fabrication Window Is Locked
Send the stackup, target impedance, material requirements, via structures, backdrill table and expected verification plan. UltroNiu engineers will identify manufacturability risks and missing fabrication controls.