When Interconnect Geometry Becomes a Microwave Performance Variable

A flip-chip assembly can meet its electrical-continuity requirement and still miss a microwave frequency target. The cause may not be an obvious open circuit. It may be a slight change in the physical separation or tilt between two chips.

That is the central engineering lesson of a 2026 study on asymmetric indium interconnects for three-dimensional superconducting quantum circuits. The researchers controlled a nominally 10 µm chip-to-chip gap and then separated mechanical accuracy, DC contact performance, and microwave loss into different measurements. [1]

Quick answer: Interconnect geometry becomes a microwave-performance variable when its height, spacing, tilt, alignment, or nearby conductive surfaces change the electromagnetic fields and coupling seen by the circuit. Low DC contact resistance demonstrates one kind of electrical integrity; it cannot, by itself, establish low microwave loss or accurate resonant frequency. The quantitative results discussed here apply to specific superconducting circuits measured at millikelvin temperatures, not to conventional room-temperature PCB assemblies.

1. Why Three-Dimensional Routing Changes the Microwave Boundary

A planar coplanar waveguide (CPW) is designed using its conductor, side gaps, reference ground, and dielectric environment. When part of that circuit is routed onto a second chip, the opposing die and the intervening vacuum gap become part of the electromagnetic environment. A mechanical assembly parameter can then affect capacitance, coupling strength, and the effective propagation characteristics.

The challenge is especially visible in superconducting quantum processors. Their control lines, readout resonators, and qubit structures need increasing interconnection density, but they are also sensitive to small changes in resonance and coupling. Moving structures onto separate chips helps routing; it introduces a new geometric degree of freedom that must be controlled. [1, 2]

It is not enough to specify a nominal gap in the assembly drawing. The post-bond gap can vary across the device because of residual tilt, local bowing, spacer deformation, particles, or compression nonuniformity. These changes are mechanical in origin but may be electrical in effect.

2. What the Asymmetric Indium Study Actually Built

Richard and colleagues, in the publicly available arXiv:2610.21435v2 preprint dated October 16, 2026, separated fabrication responsibilities between a control chip and a qubit chip. The control chip carried approximately 20 µm thick indium bumps and SU-8 polymer spacers. The qubit chip carried only approximately 200 nm thick indium pads at the bonding interfaces. [1]

This asymmetry has a specific purpose. Thick-indium lift-off and spacer lithography are kept away from the more sensitive qubit-processing surface. The design preserves a galvanic path between chips while reducing additional processing on the qubit wafer. It is a wafer-level superconducting assembly process—not a standard PCB plating, soldering, or copper-via process.

3. Gap Uniformity and Tilt Are Different Control Problems

A spacer can restrict how closely the two dies approach one another. It does not necessarily make the two surfaces parallel. In the study, specimens bonded in one compression step with spacers still showed a mean residual tilt of 209 ± 84 µrad and a reconstructed spatial RMS gap variation of 418 nm. [1]

The research team then rotated the assembly between compression steps, with four orientations separated by nominal 90° increments. In that test configuration, the mean residual tilt fell to 20 ± 12 µrad and the reconstructed spatial RMS variation fell to 64 nm. The resulting mean gap was 10.04 µm. These numbers are measured outcomes for the reported samples, not permissible tolerances for other products.

The authors also tested four larger assemblies with 14.3 × 14.3 mm chips. They reported 23 ± 8 µrad residual tilt, a mean separation of 10.08 µm, and 158 nm spatial RMS variation over the chip area. This is an important scaling check, but four assemblies do not establish high-volume process capability or long-term yield. [1]

4. Why the Same Geometry Can Shift a Microwave Frequency

Inter-chip separation changes the distribution of electric fields between the two dies. In these flip-chip circuits it affects the capacitance of transmon electrodes to the facing ground plane, as well as the effective dielectric environment of coplanar resonators. Consequently, the same nominal lithographic trace can acquire a different electrical environment after assembly.

The paper includes a simulation in which a 2 µm gap change produces roughly a 2% shift in CPW resonator frequency and a 6% change in qubit capacitance for the specific modeled device. These are not universal sensitivity coefficients; different resonator and ground geometries can respond differently. [1]

That is why the relevant acceptance parameter should be stated explicitly. If a design depends on frequency targeting, a measured chip gap may be a useful process-control variable, but only RF measurement or an appropriately correlated model can establish the associated electrical result.

5. What DC Resistance Proves—and What It Does Not

The study used a series chain of 3,810 indium contacts for cryogenic DC characterization. Below the indium superconducting transition, the authors reported a model-based upper bound of 9.71 nΩ per interconnect from the observed distribution. They also reported a critical-current lower bound above 105 mA in a separate 10-contact chain at temperatures of 1 K or below. [1]

These observations support low-resistance galvanic connectivity in those cryogenic conditions. They do not directly measure the frequency-dependent loss of a CPW transition, the local electric-field participation of interfaces, or the effect of a discontinuity on a microwave mode.

6. What the Microwave Measurements Demonstrated

For baseline resonator comparison, the authors characterized four CPW resonators on control chips and six on qubit chips at resonance frequencies spanning 4–8 GHz. Measurements were carried out at approximately 15 mK. At low photon number, the reported average internal quality factors were (0.90 ± 0.11) × 10⁶ on the control chip and (1.93 ± 0.40) × 10⁶ on the qubit chip. These values describe the complete resonators and their processing environments. [1]

A separate device contained six resonators with one to six indium transitions, plus four control-chip reference resonators. The authors modeled internal loss as a combination of control-chip loss, qubit-chip loss, and a term proportional to the number of indium transitions. Their fitted per-transition contribution was (0.54 ± 0.42) × 10⁻⁷, with R² = 0.68. Because of the small resonator population and substantial fit uncertainty, they interpreted the result as a bound of less than 1 × 10⁻⁷ per transition within the stated 1σ treatment, rather than a universal constant. [1]

The team also measured six flip-chip transmons repeatedly over 24 hours, obtaining 100 measurements per qubit and per coherence parameter. They reported an average T1 of 159 ± 14 µs and T2,echo of 294 ± 42 µs, with a separate six-qubit planar reference for T1 comparison. A hundred repeated observations on one qubit do not mean a hundred independent qubits or packages were tested.

The available evidence therefore supports a bounded conclusion: the asymmetric structure and multi-angle bonding achieved precise mechanical alignment while preserving favorable microwave and qubit performance in the tested cryogenic devices. It does not establish industrial yield, conventional RF board insertion loss, or a validated production capability at UltroNiu.

7. The Cryogenic Superconducting Boundary Is Essential

Indium becomes superconducting below approximately 3.4 K; the cited work observed an indium transition at about 3.42 K. The microwave-resonator measurements were performed near 15 mK, far below room temperature, with very low drive powers to probe the single-photon regime. [1]

At these conditions, superconducting surface and interface losses, two-level-system contributions, cryogenic packaging, and resonator photon number matter. It would be incorrect to translate the reported Qint or per-transition internal-loss bound into an ordinary 25°C PCB transmission-line loss specification—or to claim that a 4–8 GHz cryogenic resonator result proves performance to tens of gigahertz.

Earlier work on superconducting flip-chip integration likewise identified chip spacing as a variable affecting resonant frequency, impedance matching, and inter-chip coupling. That supports the broader physical interpretation, but it does not remove the temperature and architecture limits of individual experiments. [2]

8. What Transfers to RF PCB and Advanced-Interconnect Reviews

The value of this research for a microwave PCB manufacturer lies in the method of reasoning, not in copying the indium process. A PCB designer should ask which assembly dimensions are truly electrical inputs and which measurements validate the finished system.

This connects with the broader principle discussed in UltroNiu’s microwave cavity and shielding tolerance analysis: mechanical dimensions become electrical variables when they change the electromagnetic boundary condition. For the design-to-manufacturing side, see the 50-ohm RF manufacturing specification guide.

9. Pre-NPI Questions That Turn a Geometry Risk Into a Validation Plan

• Define the physical boundary: Which die, PCB, carrier, lid, spacer, launch or ground structure participates in the field distribution?
• Freeze meaningful dimensions: Which post-assembly height, lateral offset, tilt, contact and surface states have an electrical sensitivity?
• Separate test purposes: What do mechanical metrology, DC continuity and RF testing each establish?
• Specify measurement conditions: What temperature, bias, drive power, reference plane and test fixture are required?
• Track sample population: Are reported counts boards, dies, resonators, transitions, or repeated observations?
• Define approval and evidence: Which changes require renewed EM review, remeasurement or customer authorization?

A good NPI handoff is not simply a drawing with tighter tolerances. It is an agreed connection between the geometry that matters, a manufacturable process window, the measurement used to verify the electrical target, and the evidence retained for later changes.

Engineering Conclusion

The key result of the asymmetric-indium study is not that all interconnects need nanometer-class mechanical control. It is that a controlled physical interface and an electrically validated interface are related but distinct engineering deliverables. The target dimensions and measurement conditions must be chosen for the actual device.

Research References and Scope

1. [1] Richard, L., et al. Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding. arXiv:2610.21435v2, October 16, 2026. Primary preprint and methods.
2. [2] Norris, G. J., et al. Improved parameter targeting in 3D-integrated superconducting circuits through a polymer spacer process. EPJ Quantum Technology 11, article 5 (2024). Published study.
3. [3] Flip-Chip Integration of the Superconducting Quantum-Classical Circuits: Coupling Types. Advanced Quantum Technologies (2025). Supporting context for cryogenic indium interconnects.

Editorial scope: Numerical results and uncertainties belong to the cited research groups. The images in this article are original conceptual illustrations, not experimental micrographs, source-device photographs or UltroNiu test records.