Technical Parameters Table

Parameter

Capability Range

Description

Layer Count

2–32 Layers

Supports complex multilayer and HDI stack-ups

Line Width/Spacing

Min. 2.5/2.5 mil (63µm)

Fine-line imaging for dense routing

HDI Build-Up Levels

1–4+ Sequential Lamination

Microvia, buried via, and stacked via structures

Laser Microvia Diameter

Min. 0.1 mm

High-precision laser drilling for HDI interconnects

Aspect Ratio (Through-Hole)

Up to 10:1

Ensures plating uniformity in thick multilayers

Surface Finish Options

ENIG, ENEPIG, OSP, Imm. Silver, Imm. Tin

Multiple finish options for high-reliability applications

Impedance Control Tolerance

±5%

Designed for high-speed and RF circuits

Material Systems

FR-4, High-Tg, Rogers, Polyimide, Hybrid

Supports rigid and high-frequency composite materials

Stack-Up Design

3D Simulation & Dk/Df Optimization

Custom dielectric modeling for performance consistency

Component Pitch

Down to 0.25 mm

Compatible with fine-pitch BGA, CSP, and 01005 SMDs