An engineering guide to translating power-integrity requirements into manufacturable, testable and repeatable PCB requirements.

Engineering takeaway: A GPU accelerator board is not simply a heavy-copper PCB. The objective is to deliver approved voltage and transient performance across the board-to-package power path while maintaining high-speed return-path integrity, BGA manufacturability, thermal performance and controlled production evidence.

This article addresses accelerator modules, carrier boards and system-level power-distribution PCBs. It does not prescribe the design of the GPU silicon, interposer, embedded package structures or vendor-specific HBM channels. Exact current, rail, geometry and performance limits must come from the device or system design owner. [1][2]

1. Define the PCB Boundary Before Choosing the Stackup

A modern accelerator combines several interconnect domains. In designs using co-packaged HBM, the very wide GPU-to-HBM memory interface is largely implemented inside the advanced package, not routed as ordinary HBM3/3e traces across a system PCB. The system board instead carries power from the VRM into package contacts, plus external interfaces such as PCIe or other high-speed links, controls, clocking and mechanical interfaces. Architectures vary; the package and module specifications govern the actual boundary. [1][2] AMD describes the MI300-series chiplet dies as connected through an active interposer, providing a direct example of the package-level distinction [9].

This matters in a fabrication review: keep the responsibilities of package substrate, accelerator module PCB, carrier/backplane and separate power-distribution board distinct. A drawing that does not identify the board type cannot justify a generic copper-weight or via-field prescription.

Figure 1. System-board and package responsibilities (illustrative architecture, not a product layout).

2. Why GPU Power Delivery Differs from Conventional High-Current Boards

Accelerator power rails can operate at low voltage while delivering substantial current, leaving a narrow allowable voltage-error budget. Fast workload-dependent demand also introduces transient voltage droop and recovery requirements. On a dense board, the conductive path includes package contacts, via arrays, power planes, localized neck-downs and return paths; its resistance and inductance can both matter.

Unlike a stand-alone DC busbar board, the same multilayer stackup may also support loss-sensitive high-speed channels, tightly controlled impedance and dense BGA escapes. The engineer must therefore consider IR drop, thermal rise, voltage transient response, signal reference paths and manufacturing constraints together. There is no universal GPU current value, 0.8 V rail or di/dt threshold: those inputs are product-dependent.

3. Copper Weight versus High-Speed Stackup: Select, Do Not Maximize

Blanket use of very heavy copper can increase conductor cross-section, but it can also complicate fine-line etching, registration, resin fill between features, press-out thickness and overall stack symmetry. Conversely, thin copper chosen for routing density may be unsuitable for a long high-current feeder. The correct choice follows the finished conductor geometry, thermal boundary conditions, current distribution and approved stackup—not a fixed rule that every GPU power plane must be 1 oz or every feed must be 4 oz. IPC-2152 provides a framework for relating current, conductor dimensions and temperature rise. [3]

Copper inlays, local plating or extra power planes can be valid options when their manufacturing and thermal consequences are qualified. The trade-off should be resolved before the PCB stackup is released.

4. Power Planes, Partitioning and Return-Path Integrity

VRM input, GPU core and auxiliary rails may require separate power copper. But a power-plane split does not automatically break every high-speed signal return: the relevant reference plane depends on the layer geometry, coupling and routing. The priority is to keep a continuous, well-defined high-frequency return path under critical signals and avoid traversing uncontrolled reference discontinuities.

Stitching vias can connect ground reference structures, but a via belt should not be presented as a universal repair for a trace crossing a void or unrelated reference plane. If routing across a split is unavoidable, layout and SI/PI teams should evaluate the complete return path, coupling and transition geometry. Keep decoupling connections short and low inductance as permitted by BGA escape and assembly constraints.

5. BGA Power Vias, Via-in-Pad and Current Distribution

Current reaches the accelerator package through a population of power and ground connections. The required via count, finished hole size, barrel plating, capture pads and pad-to-plane connections depend on the package pin map, PCB thickness, actual rail loading and acceptable temperature rise. Avoid assuming that one nominal via diameter has a universal ampere rating.

Via-in-pad may be needed for breakout, soldering or connection-density reasons, but the fabrication drawing must distinguish filled versus plugged vias, fill material, plating/capping, planarization, void criteria and tolerances. Resin-filled and copper-capped constructions are used in industry; copper filling is a different process choice and is not automatically necessary for every high-current BGA via. IPC-4761 describes via-protection options and drawing terminology, while the agreed construction, process capability and acceptance criteria remain project-specific [7,8].

Figure 2. Via-in-pad cross-section and conceptual power/ground via field. Not to scale.

Dense via fields can challenge registration, copper distribution and local geometry. Board warpage, however, is multifactorial: material CTE, construction symmetry, panel layout, copper distribution and assembly thermal history all contribute. No single pattern should be declared the “most common” cause without production evidence.

6. Target Impedance and Transient Power Integrity: What the PCB Can Verify

A common first-pass PDN budgeting expression is Z_target = ΔV_allowable / ΔI_step, where the numerator represents the voltage deviation allocated to the relevant transient and the denominator represents a specified load-current change. This ratio is a starting design budget, not proof that a completed accelerator will meet dynamic voltage requirements. Rail tolerances must be allocated among DC regulation, transient droop, package and board effects, and measurement uncertainty. [4]

Power integrity depends on the VRM, bulk decoupling, local MLCCs, PCB planes and vias, package parasitics and on-die structures. Their frequency responses overlap, and capacitor mounting inductance or anti-resonance can create impedance peaks. A defensible sign-off combines vendor-provided models, frequency-domain analysis and time-domain load-transient verification at the appropriate reference point; board-only results do not establish die-level compliance.

Figure 3. Conceptual PDN path and evidence chain. No synthetic impedance curve or measured data are shown.

For example, a fabricator can verify agreed stackup, conductor thickness, drilled/plated via geometry and defined coupon results. The system SI/PI owner remains responsible for selecting and correlating the complete GPU rail model, transient stimuli and voltage acceptance criteria. IEEE 370-2020 is relevant to high-frequency interconnect characterization and fixture/data quality; it is not a substitute for a GPU-specific PDN acceptance specification. [6]

7. DFM from Prototype through NPI to Repeatable Production

A small prototype lot can demonstrate basic manufacturability without proving that the same stackup will hold flatness, registration and via-fill quality across production panel quantities. Risks often become more visible when panel loading, copper distribution, resin flow, sequential lamination, fill/cap plating or assembly thermal cycles change. These are engineering risks to verify, not claims that all high-current GPU boards exhibit the same failure mode.

Before the layout baseline is frozen, the design owner and fabricator should agree critical dimensions and process exclusions. During NPI, confirm measured results against those requirements and define a controlled production plan. After release, maintain revision, material and process change control so that accepted results remain tied to the qualified configuration.

Figure 4. Distinct design, NPI and production-release gates for manufacturing evidence.

8. IPC-6012 Acceptance Class and Product Reliability

IPC-6012 is a qualification and performance specification for rigid printed boards; the agreed class and any additional requirements must be specified in the purchase documentation and design package. Continuous 24/7 operation or high replacement cost may motivate more stringent acceptance or reliability testing, but does not automatically require Class 3. Class selection should reflect the application, customer requirements and risk-assessed qualification plan. [5]

Where justified, the plan may include relevant microsection, plating, thermal stress, thermal cycling, interconnect-stress or other agreed testing. Do not claim that Class 3 by itself validates power integrity, GPU lifetime or assembled-product performance. These are separate engineering and product-level questions.

9. Pre-Tapeout / Pre-NPI Manufacturing Handoff

Treat fabrication readiness as a set of approved inputs and deliverables, not merely a check that Gerber files have been exported.

Checklist before releasing manufacturing data

• Confirm which interconnects are system-PCB responsibilities and which are inside the GPU/HBM package.
• Approve finished conductor geometry, copper types, stackup and relevant power-plane neck-downs.
• Validate critical power and ground via structures against vendor pin maps and defined loads.
• Specify via-in-pad fill/cap construction and acceptance criteria rather than relying on an ambiguous generic note.
• Check high-speed reference continuity and signal return paths at plane transitions.
• Assign board-level PI evidence separately from package/die-level power integrity sign-off.
• Agree flatness, coupon, microsection and reliability verification requirements.
• Lock the acceptance class, NPI baseline, material substitutions and production change authority.

Frequently Asked Questions

Should every GPU power plane use 4 oz or heavier copper?

No. Copper thickness depends on finished geometry, allowed temperature rise, IR drop, signal-routing density and process capability. Some boards benefit from heavier copper or local reinforcement; others use multiple conventional copper planes and via arrays.

What current or di/dt value should a GPU PCB be designed for?

There is no universally valid current or transient slew rate. The responsible design team must obtain the actual rail, load-step, droop and package limits from the accelerator or system specification.

Are HBM signal traces routed on the GPU system PCB?

For co-packaged HBM architectures, the high-density GPU-to-HBM interface is mainly inside the advanced package/interposer. The system PCB still carries power and external high-speed links. Confirm the actual module architecture.

Does a via-in-pad always require copper fill?

No. Depending on hole type, assembly and current requirements, resin filling with appropriate copper capping or a validated copper-fill process may be specified. The drawing must define the construction and acceptance criteria.

Does 24/7 AI server operation require IPC-6012 Class 3?

Not automatically. The customer must define the intended class and any additional product-specific qualification evidence. Continuous service and costly downtime can influence the risk assessment.

Can a PCB manufacturer certify the full GPU PDN transient response?

Not from bare-board inspection alone. The manufacturer can validate agreed board structures and tests, while full power integrity sign-off requires the system-level rail models, package assumptions and load-transient verification.

Engineering Review Request

Planning an AI accelerator or high-current GPU PCB build? Send the approved fabrication data, intended stackup, copper and via requirements, mechanical/flatness constraints, and the rail or PDN assumptions relevant to manufacturing. UltroNiu can discuss the manufacturability and inspection plan for the specified board structures. Customer-owned SI/PI, thermal and end-product qualification remain separate approval responsibilities.

Request a Stackup & DFM Review: https://www.ultroniu.com/engineering-review.html

Technical References

[1] NVIDIA. Blackwell Architecture. https://www.nvidia.com/en-us/data-center/technologies/blackwell-architecture/

[2] AMD. AMD Instinct MI300X Platform and Accelerator Specifications. https://www.amd.com/en/products/accelerators/instinct/mi300/platform.html

[3] IPC. IPC-2152, Standard for Determining Current Carrying Capacity in Printed Board Design (official table of contents). https://www.ipc.org/TOC/IPC-2152.pdf

[4] AMD. Versal PCB Design Guide, Target Impedance. https://docs.amd.com/r/en-US/ug863-versal-pcb-design/Target-Impedance (illustrates general budgeting method; not a GPU rail specification).

[5] IPC. IPC-6012F, Qualification and Performance Specification for Rigid Printed Boards. https://www.ipc.org.cn/standards/ipc-6012

[6] IEEE Standards Association. IEEE 370-2020, Electrical Characterization of PCB and Related Interconnects at Frequencies up to 50 GHz. https://standards.ieee.org/ieee/370/6165/

[7] IPC. IPC-4761, Design Guide for Protection of Printed Board Via Structures (official IPC publication). https://www.ipc.org/TOC/IPC-4761.pdf

[8] Eurocircuits. Via Filling: Via-in-Pad Processing (manufacturing example, not the official IPC standard). https://www.eurocircuits.com/technical-guidelines/pcb-manufacturing-technology/via-filling-eurocircuits-have-invested-in-the-itc-thp-30-machine/

[9] AMD. Instinct CDNA 3 GPU Architecture: Chiplet Dies Connected through an Active Interposer. https://rocm.docs.amd.com/projects/amdsmi/en/develop/conceptual/partition.html